The row-column timing of a keyboard PCB matrix scanning circuit is essentially a cyclical process in which the microcontroller (MCU) alternates between the roles of “driving” and “reading” for each column (or row) in sequence. The core logic is as follows: only one column line is activated at any given time, after which the states of all row lines are read simultaneously to determine which key—at the intersection of a column and a row—has been pressed.
I. Standard Row-Column Scanning Timing: Column-Driven, Row-Read
Taking the most common “column-driven, row-read” architecture as an example, a complete scanning cycle consists of the following timing steps:
Step 1: Select and drive the target column. The microcontroller sets the $k$-th column line (Column $k$) to a high (or low, depending on the circuit logic) voltage level, while placing all other unselected column lines into an inactive state (such as a high-impedance state or an opposite voltage level). The purpose of this step is to send an “interrogation signal” exclusively to all keys located on Column $k$.
Step 2: Wait for signal stabilization (Settling Time). Following the transition of the column line’s voltage level, the signal requires a brief moment to stabilize due to parasitic capacitance and resistance within the circuitry. The firmware must incorporate a “settling time” to ensure that the row lines are not read before the voltage levels have stabilized, which could otherwise lead to erroneous readings. If the matrix incorporates isolation diodes—and unselected columns are driven to an inactive voltage level rather than a high-impedance state—this settling time can be significantly reduced or even eliminated.
Step 3: Read the states of all row lines in parallel. Once the signal has stabilized, the microcontroller reads the voltage levels of all row lines (Row 1 through Row $N$) simultaneously. If a key located at the intersection of Column $k$ and a specific row (e.g., Row $x$) is pressed, the physical closure of that key conducts the voltage level from Column $k$ to Row $x$. Consequently, the $x$-th bit in the data read from the row lines will appear in an “active” state. Because all row lines are read at once, the status of $N$ keys can be detected within a single clock cycle.
Step 4: Proceed to the next column and repeat the cycle. Once column $k$ has been read, the controller disables the driver for column $k$, selects column $k+1$, and repeats the “drive-wait-read” sequence. This process continues until all $M$ column lines have been scanned, completing one full matrix scan cycle.
II. Special Timing for Magnetic-Switch Keyboards: Decoupling Scanning from Sampling
For magnetic-switch keyboards, the matrix scanning logic must also account for the sampling of analog signals. Magnetic switches utilize Hall-effect sensors, which output continuous analog voltages rather than simple on/off (binary) signals. Consequently, the timing sequence is typically divided into two phases: “channel selection” and “ADC sampling.”
In a hardware-based sequential scanning scheme, a DMA controller follows a predefined task chain to periodically switch the channels of a multiplexer (MUX), connecting the Hall-effect sensor of a target row (or column) to an analog-to-digital converter (ADC). Once the MUX has switched and the signal has stabilized, the ADC begins sampling and quantizing the analog signal, storing the resulting data in a buffer. This means that the “scanning timing” for magnetic switches encompasses not only the switching of digital logic levels but also the time windows required for analog signal stabilization and ADC conversion. To balance power consumption with responsiveness, magnetic-switch keyboards often employ a dual-list scanning strategy: keys that are not currently pressed are scanned at a slower rate (with a longer interval, $T_1$), while any key whose analog value crosses a specific motion threshold is moved to a high-speed scanning list, where it is sampled with much greater frequency (a shorter interval, $T_2$).
III. The Impact of Timing Parameters on Keyboard Performance
The cadence of row and column scanning directly determines a keyboard’s input latency and its resistance to misinterpretation (false inputs).
Scan Cycle and Latency: The time required to complete a full scan of all columns—the “scan cycle”—sets the lower bound for the keyboard’s polling interval. To ensure that rapid keystrokes are not missed, the scan cycle is generally kept within 20 to 40 milliseconds. If the scanning process is too slow, quick key presses occurring between consecutive scans may be overlooked, or two keys pressed in rapid succession might be incorrectly registered as having been pressed simultaneously (a phenomenon known as key transposition). However, in competitive keyboards with an 8K polling rate, this cycle is compressed down to the microsecond level.
Debounce Window: When a mechanical switch closes, it undergoes physical vibration, generating a series of rapid on-off pulses. Consequently, upon detecting a change in the state of a row line, the firmware does not report it immediately. Instead, it waits for a “debounce period” (typically 5–10 milliseconds) to ensure the signal level has stabilized before registering a valid keypress. This debounce window is a deliberate “delay” introduced into the sequential logic to ensure reliability.
Ghosting and Diode-Based Timing: In a standard matrix lacking diodes, pressing three keys that form the corners of a rectangle can cause current to flow back through a “parasitic path,” leading the microcontroller to incorrectly register a “ghost key”—a key that was never actually pressed. To resolve this at the logic level, a matrix with isolation diodes incorporates a unidirectional diode in series with each switch, effectively blocking reverse current. From a timing perspective, the presence of these diodes allows the microcontroller to disable ghost-key detection algorithms and even utilize more aggressive timing parameters (such as significantly shorter stabilization times), thereby enhancing scanning efficiency.
